A group of technology companies that includes AMD, ARM, Dell EMC, IBM, HPE, Micron, Samsung, Seagate, SK hynix, Western Digital, and others, created the Gen-Z Consortium to develop and commercialize a new bus interconnect technology that’s optimized for next-generation fast storage technology. Intel doesn't appear to be part of the consortium as of right now.
Gen-Z Consortium Members
Architects built today’s computer designs around the idea that storage is slow and persistent, while memory is fast and volatile. However, as we’ve already seen with Intel and Micron’s 3D XPoint technology, new storage technologies are starting to appear that can work as both high-performance storage and non-volatile memory. That means previous architectural assumptions that have worked in the past are no longer optimal for future use-cases.
"The increased computing demands of artificial intelligence, machine learning, advanced analytics and other Cognitive Era workloads requires greater __hardware performance and innovation," said Brad McCredie, Fellow and Vice President of POWER Development at IBM.
Why A New Bus Is Needed
According to the Gen-Z consortium, per-core memory bandwidth is declining while per-core memory capacity is flat. The number of cores in data centers continues to grow at a fast pace, and memory and bandwidth can barely keep up.
Data is also on an explosive growth path due to the rise of the “Internet of Things,” and the __hardware resources limit how fast and accurately the data can be analyzed if they can't keep up.
"As the industry moves toward the 3rd platform new open innovations are required to enable infrastructure support of massive data, billions of IoT devices, and cloud native applications," said John Roese, CTO of the Infrastructure Solutions Group at Dell EMC.
The consortium believes that an open architecture for a next-generation interconnect technology is necessary as memory tiers become increasingly more important. Rack-scale composability also requires a high-bandwidth, low-latency memory fabric. The Gen-Z protocol also promises to work with existing operating systems without changes, which should help increase adoption.
Memory/Storage Evolution In Systems
The consortium sees memory tiers evolving from being represented mainly by just a reasonable amount of RAM and a high amount of SSD/HDD storage to using little RAM in combination with faster on-package memory (OPM) and a small amount of SSD/HDD storage. “Storage class memory” (SCM) would represent the bulk of storage/memory.
Memory-Speed Communication
The Gen-Z fabric protocol will be “memory-semantic,” which means it will handle all communications as memory operations, such as the load/store, put/get, and atomic operations normally used by the CPU.
Memory semantics are optimal at sub-microsecond latencies from CPU load command to register store, unlike storage access that is block-based, uses interrupts, and is managed by complex software stacks.
Gen-Z Fabric Benefits
The Gen-Z consortium designed the fabric protocol to offer three main benefits.
1. High-Performance/Low-Latency
The Gen-Z protocol has high-performance with support for hundreds of GB/s bandwidth and low sub-100ns latency. It also supports simple read/write memory-semantic operations.
2. Advanced Workloads And Technologies
The new fabric protocol allows real-time analytics, enables data centric and hybrid computing, supports scalable memory pools for in-memory applications, and it can abstract the media interface from the SoC to unlock new media innovation.
3. Compatibility/Security
The new protocol promises secure end-to-end connectivity from one node to another, even at rack scale. The protocol has high software compatibility as it won’t require OS changes, and users can implement the technology economically.
No comments:
Post a Comment